Z800 CPU の全貌 9ページ
命令セット(つづき)
入出力グループ フラグ
   命令  アドレッシングモード     処理
IN dst , (C) dst = R, RX, DA, X, RA,
  SR, BX
Input
dst(C)
IN A , (n) Input Accumulator
A(n)
IN[W] HL , (C) Input HL
HL(C)
IND Input and Declement (BYTE)
(HL)(C)
BB - 1
HLHL - 1
INDW Input and Declement (WORD)
(HL)(C)
BB - 1
HLHL - 2
INDR Input, Declement and Repeat
(BYTE)

B=0 になるまで繰り返し
  (HL)(C)
  BB - 1
  HLHL - 1
INDRW Input, Declement and Repeat
(WORD)

B=0 になるまで繰り返し
  (HL)(C)
  BB - 1
  HLHL - 2
INI Input and Inclement (BYTE)
(HL)(C)
BB - 1
HLHL + 1
INIW Input and Inclement (WORD)
(HL)(C)
BB - 1
HLHL + 2
INIR Input, Inclement and Repeat
(BYTE)

B=0 になるまで繰り返し
  (HL)(C)
  HLHL + 1
  BB - 1
INIRW Input, Inclement and Repeat
(WORD)

B=0 になるまで繰り返し
  (HL)(C)
  BB - 1
  HLHL + 2
OUT (C) , src src = R, RX, DA, X, RA,
  SR, BX
Output
(C)src
OUT (n) , A Output Accumulator
(n)A
OUT[W] (C) , HL Output HL
(C)HL
OUTD Output and Declement (BYTE)
BB - 1
(C)(HL)
HLHL - 1
OUTDW Output and Declement (WORD)
BB - 1
(C)(HL)
HLHL - 2
OUTDR Output, Declement and Repeat
(BYTE)

B=0 になるまで繰り返し
  BB - 1
  (C)(HL)
  HLHL - 1
OUTDRW Output, Declement and Repeat
(WORD)

B=0 になるまで繰り返し
  BB - 1
  (C)(HL)
  HLHL - 2
OUTI Output and Inclement (BYTE)
BB - 1
(C)(HL)
HLHL + 1
OUTIW Output and Inclement (WORD)
BB - 1
(C)(HL)
HLHL + 2
OUTIR Output, Inclement and Repeat
(BYTE)

B=0 になるまで繰り返し
  BB - 1
  (C)(HL)
  HLHL + 1
OUTIRW Output, Inclement and Repeat
(WORD)

B=0 になるまで繰り返し
  BB - 1
  (C)(HL)
  HLHL + 2
TSTI (C) Test Input
Ftest(C)
CPU制御グループ フラグ
   命令  アドレッシングモード     処理
DI Int Int = E6, E5, E4, E3, E2,
  E1, E0
Disable Interrupt
If Ei then
  MSR(i)0
Otherwise
  MSR 0__60
EI Int Int = E6, E5, E4, E3, E2,
  E1, E0
Enable Interrupt
If Ei then
  MSR(i)1
Otherwise
  MSR 0__61
HALT Halt
CPU Halts
IM p p = 0, 1, 2, 3 Interrupt Mode Select
Interrupt Modep
LD A , src src = I, R Load I or R Register from
Accumulator

Asrc
LD dst , A dst = I, R Load Accumulator from
I or R Register

dstA
LDCTL dst , src dst =
src =
or
dst =
src =
(C), USP
HL, IX, IY

HL, IX, IY
(C), USP
Load Control
dstsrc
NOP No Operation
PCACHE Purge Cache
All cache entries
invalidated
RETI Return from Interrupt
PC(SP)
SPSP + 2
RETIL Return from Non-maskable
Interrupt

PS(SP)
SPSP + 4
RETN Multiply (BYTE)
Return from Interrupt

PC(SP)
SPSP + 2
MSR(0-7)IFF(0-7)
拡張命令グループ フラグ
   命令  アドレッシングモード     処理
EPUM src src = IR, DA, X, RA, SR,, BX Load EPU from Memory
EPUtemplate
EPUsrc
MEPU dst dst = IR, DA, X, RA, SR,, BX Load Memory from EPU
EPUtemplate
dstEPU
EPUF Load Accumulator from EPU
EPUtemplate
AEPU
EPUI EPU Internal Operation
EPUtemplate
page 9