Z800 CPU の全貌 7ページ
命令セット(つづき)
ブロック転送および検索グループ フラグ
   命令  アドレッシングモード     処理
CPD Compare and Decrement
A - (HL)
HLHL - 1
BCBC - 1
CPDR Compare and Decrement & Repeat
A - (HL)
HLHL - 1
BCBC - 1
以上を BC=0 または A=(HL) に
なるまで繰り返す
CPI Compare and Increment
A - (HL)
HLHL + 1
BCBC - 1
CPIR Compare and Increment & Repeat
A - (HL)
HLHL + 1
BCBC - 1
以上を BC=0 または A=(HL) に
なるまで繰り返す
LDD Load and Decrement
(DE)(HL)
DEDE - 1
HLHL - 1
BCBC - 1
LDDR Load and Decrement & Repeat
(DE)(HL)
DEDE - 1
HLHL - 1
BCBC - 1
以上を BC=0 になるまで繰り返す
LDI Load and Increment
(DE)(HL)
DEDE + 1
HLHL + 1
BCBC - 1
LDIR Load and Increment & Repeat
(DE)(HL)
DEDE + 1
HLHL + 1
BCBC - 1
以上を BC=0 になるまで繰り返す
8ビット算術&論理演算グループ フラグ
   命令  アドレッシングモード     処理
ADC [A] , src src = R, RX, IM, IR, DA, X,
 SX, RA, SR, BX
Add With Carry (BYTE)
AA + src + C
ADD [A] , src src = R, RX, IM, IR, DA, X,
 SX, RA, SR, BX
Add (BYTE)
AA + src
AND [A] , src src = R, RX, IM, IR, DA, X,
 SX, RA, SR, BX
And
AA AND src
CP [A] , src src = R, RX, IM, IR, DA, X,
 SX, RA, SR, BX
Compare (BYTE)
A - src
CPL [A] Complement Accumulator
ANOT A
DAA [A] Decimal Adjust Accumulator
ADecimal Adjust A
DEC dst dst = R, RX, IR, DA, X,
 SX, RA, SR, BX
Decrement (BYTE)
dstdst - 1
DIV [HL,] src src = R, RX, IR, DA, X,
 SX, RA, SR, BX
Devide (BYTE)
AHL÷src
Lremainder(余り)
DIVU [HL,] src src = R, RX, IR, DA, X,
 SX, RA, SR, BX
Devide Unsigned (BYTE)
AHL÷src
Lremainder(余り)
EXTS [A] Extend Sign (BYTE)
LA
If A(7)=0 then H00
If A(7)=0 else HFF
INC dst dst = R, RX, IR, DA, X,
 SX, RA, SR, BX
Increment (BYTE)
dstdst + 1
MULT [A,] src src = R, RX, IM, IR, DA,
 X, SX, RA, SR, BX
Multiply (BYTE)
HLA × src
MULTU [A,] src src = R, RX, IM, IR, DA,
 X, SX, RA, SR, BX
Multiply Unsigned (BYTE)
HLA × src
NEG [A] Negate Accumulator
A-A
OR [A,] src src = R, RX, IM, IR, DA, X,
 SX, RA, SR, BX
OR
AA OR src
SBC [A,] src src = R, RX, IM, IR, DA, X,
 SX, RA, SR, BX
Subtract With Carry (BYTE)
AA - src - C
SUB [A,] src src = R, RX, IM, IR, DA, X,
 SX, RA, SR, BX
Subtract
AA - src
XOR [A,] src src = R, RX, IM, IR, DA, X,
 SX, RA, SR, BX
Exclusive OR
AA XOR src
16ビット算術演算 フラグ
   命令  アドレッシングモード     処理
ADC dst , src dst =
src =
or
dst =
src =
or
dst =
src =
HL
BC, DE, HL, SP

IX
BC, DE, IX, SP

IY
BC, DE, IY, SP
Add With Carry (WORD)
dstdst + src + C
ADD dst , src dst =
src =
or
dst =
src =
or
dst =
src =
HL
BC, DE, HL, SP

IX
BC, DE, IX, SP

IY
BC, DE, IY, SP
Add (WORD)
dstdst + src
ADD dst , A dst = HL, IX, IY Add Accumulator to
Addressing Register

dstdst + A
ADDW [HL] , src src = RR*, IM, DA, X, RA Add Word
HLHL + src
CPW [HL] , src src = RR*, IM, DA, X, RA Compare (WORD)
HL - src
DECW dst src = RR*, IR, DA, X, RA Declement (WORD)
dstdst - 1
DIVUW [DEHL] , src src = RR, IM, DA, X, RA Divide Unsigned (WORD)
HLDEHL÷src
DEremainder(余り)
DIVW [DEHL] , src src = RR, IM, DA, X, RA Divide (WORD)
HLDEHL÷src
DEremainder(余り)
EXTS HL Extend Sign (WORD)
If H(7)=0 then DE0000
If H(7)=0 else DEFFFF
INCW dst dst = RR, IR, DA, X*, RA Increment (WORD)
dstdst + 1
MULTUW [HL] , src src = RR, IM, DA, X, RA Multiply Unsigned (WROD)
DEHLHL×src
MULTW [HL] , src src = RR, IM, DA, X, RA Multiply (WROD)
DEHLHL×src
NEG [HL] Negate HL
HL-HL
SBC dst , src dst =
src =
or
dst =
src =
or
dst =
src =
HL
BC, DE, HL, SP

IX
BC, DE, IX, SP

IY
BC, DE, IY, SP
Subtract With Carry (WORD)
dstdst - src - C
SUBW [HL] , src src = RR*, IM, DA, X*, RA Subtract (WORD)
HLHL - src
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